Hardware designs usually employ a description technique called RTL. The RTL description is based on “synchronization at clocks”. Simulation of the RTL description by software takes much time because of huge number of actions including the behavior of hardware to be operated. The RTL-description simulation could be faster if “synchronization at clocks” were not required. This is because it is enough for software that hardware (LSI) exhibits input/output responses, irrespective of whether or not the hardware has synchronization at internal clocks.
Recently proposed but not so popular is high-level synthesis, a technique to convert hardware operations described with a programming-language-like description technique under no consideration of hardware clocks into RTL description with a specific tool.
In contrast, behavior description requires fewer amount of description than RTL, achieving high productivity and high-speed simulation like above, thus shorting design and verification turnaround time at the behavior level.
The behavior description does not allow exact timing verification due to unsynchronization at clocks, nevertheless, still allows functional verification by simulation at the hardware behavior level and offers highly-functional stubs when viewed from software.
As discussed, the RTL description is based on “synchronization at clocks”, thus RTL simulation on computer takes much time. On the contrary, the behavior description describes hardware operations (behavior) with no description of synchronization at clocks. The latter description technique allows high-speed simulation under no consideration of exact synchronization.
Therefore, conversion from hardware-design description which is RTL only at present, into behavior is feasible for high-speed simulation.
There are several tools for converting the RTL description into a computer language for software description, such as, Language C. One of them is Verilog2C++ (trademark).
These known techniques convert hardware RTL description in parallel processing into a computer language in serial processing.
For example, Verilog2C++ divides the RTL description into “register” and “combinational circuit/latch”. Verilog2C++ sequentially converts the RTL description into source codes, a programming language executable on computer, while computational results at “combinational circuit/latch” are being transferred to “register” to produce outputs.
In detail, for example, as shown in FIG. 19, hardware is divided into an externally-accessible controllers A and data paths B each under control by signals from the corresponding controller A.
The controllers A and the data paths B are constituted by a register and a combinational circuit (or latch).
In detail, a hardware circuitry is constituted by a controller A and a data path (not shown) at a clock C1. Another hardware circuitry is constituted by a controller A and a data path B at a clock C2. Still another hardware circuitry is constituted by a controller A and a data path B at a clock C3, and so on.
The combinational circuit is equipped with a control-signal output unit and a next-state determining unit for outputting a computational result of the combinational circuit to a state register in a controller A or the register in a data path B.
The hardware circuitries operate in parallel while signals are being input to or output from the controllers A and the data paths B at respective clock timings.
In operation, a specific value input to the register (state register) in the controller A at the timing of clock C1 triggers a specific processing at the combinational circuit in the controller A in accordance with a value output from the state register.
A control signal is output from the control-signal output unit in the controller A to the register in the data path B at the timing of clock C2, a register value in the unit B being sent to the combinational circuit in the unit B for a specific processing.
Also at the same timing of clock C2, a computational result at the combinational circuit in the controller A is sent from the next-state determining unit in the controller A to the state register as a new value.
At the succeeding timing of clock C3, a control signal from the controller A and a computational result at the combinational circuit in the data path B are supplied to the register in the data path B, and a computational result at the combinational circuit in the controller A is supplied from the control-signal output unit in the controller A to the state register as a new value.
The hardware shown in FIG. 19 repeats these operations.
Verilog2C++ sequential processing of the RTL description for the hardware shown in FIG. 19, however, causes data dependency from “register” to “combinational circuit/latch” when the output of a latter-stage “register” is input to a former-stage “combinational circuit/latch”, thus redundant processing unnecessary in operation but undetectable in the RTL description only remaining in a resultant program-language source.